In digital IC design flow, functional verification usually takes 70% of the total design cycle, and 95% functional verification is based on simulation. Therefore time for simulation has a significant impact on an IC chip's TTM (time to market), and thus simulation speedup is very important for success of IC chip design.
At present common simulation tools in the industry include VCS by Synopsys company, NCSIM by Cadence company, etc. The IC simulation verification flow is as below: first, converting RTL description of the circuit into a format recognizable to some simulator, i.e. model processing; then, loading a model to a simulator. Later, test cases are applied at the input port, and the circuit behavior is simulated by the simulator; in the meanwhile, the circuit behavior is monitored using a reference model, and if the simulated circuit behavior does not match the reference model, then errors occur and are reported to verification engineer. Test cases are usually organized into test suites and run in batch mode. Successful test suites run require all test cases included pass. This regression process takes the longest simulation time.
Circuit descriptions for RTL (register-transfer level) simulation and gate-level simulation are descriptions of different abstraction levels of a digital circuit. Taking a simple AND gate as an example, the RTL description may be C=A & B, while the gate-level description is a concrete AND gate. All descriptions of these different abstraction levels may be regarded as descriptions of circuit diagram.
RTL simulation/gate-level simulation above includes a two-value simulation and a multi-value simulation. The two-value simulation refers to represent one logical bit with only binary value 0 and 1; the multi-value simulation refers to represent one logic bit by multiple values such as 0/1/X, etc. For example, in the above example of a simple AND gate, a truth table of the two-value simulation C=A+B is shown as Table 1.
TABLE 1CAB000111001010
FIG. 2 shows a gate-level circuit model corresponding to the simple AND gate two-value simulation.
In the above example of a simple AND gate, a truth table of one implementation Cx=Ax+Bx of the multi-value simulation is shown as Table 2.
TABLE 2ABCAAXBBXCCX0000000000100011000X0000100100110000111→1111111XX110101X00010000X1X011101XXX010101
FIG. 3 shows a gate-level circuit model corresponding to the simple AND gate's multi-value simulation under the implementation in Table 2.
Real digital circuit run in multi-value so multi-value simulation is more accurate than 2-value simulation, while 2-value simulation runs much faster and has better performance. Table 3 shows a comparison between the two-value simulation and the multi-value simulation in modeling time, model scale and regression time during GPS-8 path digital IC design, wherein GPS-8 path digital IC design is merely a circuit having ordinary complexity. As seen from Table 3, the multi-value simulation model is complex; since the model scale is much larger, more memories are needed, and the regression time is longer.
TABLE 3multipletwo-valuemulti-valuerelationship (multi-simulationsimulationvalue/two-value)modeling time 90 seconds 181 seconds2 timesmodel scale10 M gate30 M gate2 timesregression time237 seconds1833 seconds8 times